Ionizing radiation such as alpha particles have the unfortunate ability to change the electrical state of electronic devices, often causing soft errors that may prevent such devices from operating properly. Often times designers will attempt to soft-error-proof an electronic device by employing redundancy coupled with voting circuitry in their designs to ensure that errant behavior is unlikely. Thus, rather than using a single logic circuit to compute a result, multiple redundant logic circuits are used, and the results are compared by separate voting circuitry to determine the correct result from among the results output by the redundant logic circuits.
Redundant circuitry, however, occupies valuable area on an integrated circuit chip and often increases power consumption substantially. This area and power consumption increase may also reduce the overall performance of an electronic device, since clock frequency may need to be reduced for a variety of reasons, including the need to accommodate the longer wires needed for larger circuit areas.
Redundant circuitry may be employed at a number of levels within the design of an electronic device, including, for example, within an execution unit of a processor. An execution unit constitutes the logic that executes the instructions that are supplied to a processor. And, whereas processors once included only a single execution unit, given the increased focus on parallelism in modern processor architectures, an execution unit is often one of many execution units that may be present on a given integrated circuit chip.
For example, at the chip level, multiple processor cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations, e.g., fixed point or floating point operations. Pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
Particularly with pipelined execution units, the circuit area required to implement redundant circuitry within certain stages of a pipeline, as well as the additional latency required to implement voting, can have an adverse impact on both the overall area and the performance of an execution unit. Furthermore, when multiple execution units are used in a given design, the adverse impacts are compounded.
Another problem experienced in many execution units is that of inefficient execution of instructions within pipelines due to inter-instruction dependencies. While pipelining often improves performance, pipelining is most efficient when the instructions processed by a pipeline are not dependent on one another, e.g., where a later instruction does not use the result of an earlier instruction. Whenever an instruction operates on the result of another instruction, typically the later instruction cannot enter the pipeline until the earlier instruction has exited the pipeline and calculated its result. The later instruction is said to be dependent on the earlier instruction, and stalling the later instruction waiting for the result of an earlier instruction is said to introduce “bubbles,” or cycles where no productive operations are being performed, into the pipeline.
One technique that may be used to extract higher utilization from a pipelined execution unit and remove unused bubbles is to introduce multithreading. In this way, other threads are able to issue instructions into the unused slots in the pipeline, which drives the utilization and hence the aggregate throughput up. Another popular technique for increasing performance is to use a single instruction multiple data (SIMD) architecture, which is also referred to as ‘vectorizing’ the data. In this manner, operations are performed on multiple data elements at the same time, and in response to the same SIMD instruction. A vector execution unit typically includes multiple processing lanes that handle different datapoints in a vector and perform similar operations on all of the datapoints at the same time. For example, for an architecture that relies on quad(4)word vectors, a vector execution unit may include four processing lanes that perform the identical operations on the four words in each vector. The aforementioned techniques may also be combined, resulting in a multithreaded vector execution unit architecture that enables multiple threads to issue SIMD instructions to a vector execution unit to process “vectors” of data points at the same time. In addition, multiple execution units may be used to permit independent operations to be performed in parallel, further increasing overall performance.
Despite all efforts to minimize the presence of bubbles in an execution pipeline, however, some bubbles are still inevitably created when executing most instruction streams. Furthermore, in addition to the reduction in performance due to bubbles being present in stages in a execution unit pipeline, the stages within which such bubbles reside still often incur some switching even though no productive work is being performed. Also, from the standpoint of power consumption, it is often the latches in a pipeline stage that draw the most power. Consequently, the switching of latches and other circuitry in pipeline stages where bubbles are present is often the source of unneeded power consumption.
Therefore, a need continues to exist in the art for a manner of protecting a circuit design from the adverse effects of ionizing radiation without the increased circuit area and decreased performance traditionally associated with redundant logic, as well as for a manner of reducing the adverse impact of bubbles within a pipelined execution unit.